TSR=1, SRET executed in S-mode does not raise an exception

[fly-1011]

Bug Description:

TSR is bit 22 of the mstatus CSR. According to the RISC-V privileged specification:

The TSR (Trap SRET) bit is a WARL field that supports intercepting the supervisor exception return
instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode will raise an
illegal-instruction exception. When TSR=0, this operation is permitted in S-mode. TSR is read-only 0
when S-mode is not supported.

In NutShell, when TSR=1 and the core is running in S-mode, executing an SRET instruction at pc=0x80000050 does not raise an illegal-instruction exception.
Test program and log information: test_TSR.zip

Inconsistent information:

Environment:

NutShell: commit e315a27