From 43942e06d2784647b659d9ed318a131a621cc2d6 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Wed, 17 Jun 2026 19:11:34 +0530 Subject: [PATCH] EDAC/qcom: Make irq configuration optional MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Shikra, the ECC interrupt configuration—enabling Tag/Data RAM interrupts and setting error thresholds—is already performed by the DSF (DDR System Firmware) before the kernel driver probes. Calling qcom_llcc_core_setup() would redundantly reconfigure these registers. Set the irq_configured flag in shikra_cfg to skip the redundant kernel-side interrupt enable register writes in qcom_llcc_core_setup(). Signed-off-by: Faiyaz Mohammed --- drivers/soc/qcom/llcc-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 273367f88f70..41523aa4d4a4 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -4325,6 +4325,7 @@ static const struct qcom_llcc_config shikra_cfg[] = { .size = ARRAY_SIZE(shikra_data), .reg_offset = llcc_v2_1_reg_offset, .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + .irq_configured = true, }, };