From df503ac38fc65e870e82953bccefb87aae4948c4 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 29 May 2026 19:42:31 +0530 Subject: [PATCH 1/3] FROMLIST: soc: qcom: llcc: Add configuration data for Shikra SoC Add Last Level Cache table and configs for the Shikra SoC. Link: https://lore.kernel.org/all/20260531-shikra_llcc_conf-v1-1-fa405f5a2404@oss.qualcomm.com/ Signed-off-by: Komal Bajaj Signed-off-by: Anurag Pateriya --- drivers/soc/qcom/llcc-qcom.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 13e1742672945..357dcd86c7f8a 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1775,6 +1775,20 @@ static const struct llcc_slice_config sdm845_data[] = {{ }, }; +static const struct llcc_slice_config shikra_data[] = { + { + .usecase_id = LLCC_ECC, + .slice_id = 26, + .max_cap = 256, + .priority = 3, + .fixed_size = true, + .bonus_ways = 0x3, + .cache_mode = 0, + .activate_on_init = true, + .vict_prio = true, + }, +}; + static const struct llcc_slice_config sm6350_data[] = { { .usecase_id = LLCC_CPUSS, @@ -4006,6 +4020,15 @@ static const struct qcom_llcc_config sdm845_cfg[] = { }, }; +static const struct qcom_llcc_config shikra_cfg[] = { + { + .sct_data = shikra_data, + .size = ARRAY_SIZE(shikra_data), + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, +}; + static const struct qcom_llcc_config sm6350_cfg[] = { { .sct_data = sm6350_data, @@ -4163,6 +4186,11 @@ static const struct qcom_sct_config sdm845_cfgs = { .num_config = ARRAY_SIZE(sdm845_cfg), }; +static const struct qcom_sct_config shikra_cfgs = { + .llcc_config = shikra_cfg, + .num_config = ARRAY_SIZE(shikra_cfg), +}; + static const struct qcom_sct_config sm6350_cfgs = { .llcc_config = sm6350_cfg, .num_config = ARRAY_SIZE(sm6350_cfg), @@ -4954,6 +4982,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfgs }, { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfgs }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfgs }, + { .compatible = "qcom,shikra-llcc", .data = &shikra_cfgs }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfgs }, { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfgs }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfgs }, From 234030fb4824309f9e260aa96832ab6d45e71006 Mon Sep 17 00:00:00 2001 From: Anurag Pateriya Date: Thu, 18 Jun 2026 17:08:39 +0530 Subject: [PATCH 2/3] PENDING: arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm Add gpio-reserved-ranges property to the tlmm node for all three Shikra EVK variants (CQM, CQS, IQS) to mark GPIOs used by the SoC internally and not available for general use. Signed-off-by: Anurag Pateriya --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 2 ++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 2 ++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 7685856d097eb..8b0aaf63903f7 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -504,6 +504,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + dmic_eldo_en_default: dmic-eldo-default-active-state { pins = "gpio71"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 3fe039581c689..3ff05b581ba53 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -426,6 +426,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + dmic_eldo_en_default: dmic-eldo-default-active-state { pins = "gpio71"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 76c0fd4513382..98ab8380a3178 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -504,6 +504,8 @@ }; &tlmm { + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; + dmic_eldo_en_default: dmic-eldo-default-active-state { pins = "gpio71"; function = "gpio"; From 116d8ceaea18979000c168bbb3081d8bd90c57e3 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Wed, 17 Jun 2026 19:11:34 +0530 Subject: [PATCH 3/3] PENDING: soc: qcom: llcc: Skip ECC interrupt setup on Shikra, pre-configured by DSF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Shikra, the DDR System Firmware (DSF) configures ECC interrupt routing before the kernel driver probes — it enables Tag/Data RAM interrupts and programs error thresholds in the LLCC interrupt-enable registers. Set irq_configured in shikra_cfg so that qcom_llcc_edac_probe() skips calling qcom_llcc_core_setup(), which would otherwise overwrite the firmware-managed register state with redundant writes. Signed-off-by: Faiyaz Mohammed Signed-off-by: Anurag Pateriya --- drivers/soc/qcom/llcc-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 357dcd86c7f8a..4185be4b054f6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -4026,6 +4026,7 @@ static const struct qcom_llcc_config shikra_cfg[] = { .size = ARRAY_SIZE(shikra_data), .reg_offset = llcc_v2_1_reg_offset, .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + .irq_configured = true, }, };