[NV]dsr1-fp4-b200-sglang: add DPA PDL lane#1792
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Reviewed by Cursor Bugbot for commit 4e4e9d3. Configure here.
| - { tp: 4, ep: 4, conc-start: 1, conc-end: 128 } | ||
| - { tp: 8, ep: 8, conc-start: 1, conc-end: 128 } | ||
| - { tp: 4, ep: 4, conc-start: 1, conc-end: 256 } | ||
| - { tp: 8, ep: 8, conc-list: [1] } |
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Single-node conc-list breaks sweep
High Severity
The TP8/EP8 search-space rows now use conc-list: [1] instead of a conc-start/conc-end range. For single-node fixed-seq-len, generate_full_sweep still reads only conc-start and conc-end, so matrix generation fails on those rows and TP8 benchmarks for this config are not scheduled.
Additional Locations (1)
Reviewed by Cursor Bugbot for commit 4e4e9d3. Configure here.
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=27579102530 |
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@claude add PR description |
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/reuse-sweep-run |
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Claude finished @hshrivastava-droid's task in 1m 24s —— View job Adding PR Description
PR description has been added with a structured summary covering the three changed files: config matrix updates, script DPA support, and perf-changelog entry. |
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@functionstackx could you please review this |


Summary
Adds a data-parallel attention (DPA) benchmark lane for the DeepSeek-R1 FP4 B200 SGLang (
dsr1-fp4-b200-sglang) fixed-sequence-length recipe and retunes the concurrency sweep matrix.Changes
Config (
.github/configs/nvidia-master.yaml)lmsysorg/sglang:v0.5.12-cu130→lmsysorg/sglang:v0.5.12.post1dp-attn: true, conc 64–256Script (
benchmarks/single_node/fixed_seq_len/dsr1_fp4_b200.sh)DP_ATTENTIONenv var (defaultfalse) with input validationDP_ATTENTION=true, launches SGLang with:--data-parallel-size=$TP)--enable-dp-attention,--enable-dp-attention-local-control-broadcast,--enable-dp-lm-head--enable-prefill-delayer,--schedule-conservativeness 3.33SGLANG_RADIX_FORCE_MISS=1env var--disable-radix-cachewith--disable-piecewise-cuda-graphPerf Changelog (
perf-changelog.yaml)dsr1-fp4-b200-sglang