Skip to content
View jayjain2365's full-sized avatar

Block or report jayjain2365

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
jayjain2365/README.md

💫 Hii Jay Jain here!

About Me

Electronics Engineering student with strong interest in VLSI, RTL Design, and Digital System Design.
Currently focused on building practical projects in Verilog and SystemVerilog, including RISC processors, pipelined architectures, and digital design modules.

Areas of Interest

  • RTL Design
  • ASIC Verification
  • Digital Electronics
  • Computer Architecture
  • FPGA Design
  • RISC-V Architecture

Technical Skills

  • Verilog HDL
  • SystemVerilog
  • Digital Design
  • Computer Organization & Architecture
  • GTKWave
  • Vivado
  • ModelSim
  • Cadence Virtuoso
  • EDA playground
  • microcontrollers (Arduino, ESP8266, ESP32)

Current Projects

  • 8-bit RISC CPU
  • RISC-V Pipelined Processor
  • FSM based projects

Currently Learning

  • Advanced RTL Design
  • ASIC Verification Concepts
  • SystemVerilog Assertions
  • UVM Basics

Goal

To build strong expertise in RTL Design and Verification while developing industry-level VLSI projects.

🌐 Socials:

Instagram LinkedIn email HDLBits

💻 Tech Stack:

HDL & Verification

Verilog SystemVerilog UVM RTL Design ASIC Verification Digital Design RISC-V FPGA

EDA Tools

Vivado ModelSim GTKWave Cadence Virtuoso EDA Playground

Programming Languages

AssemblyScript Python JavaScript HTML5 CSS3 Arduino

📊 GitHub Stats:



Pinned Loading

  1. RISC-V-Pipelined-Processor-Verilog- RISC-V-Pipelined-Processor-Verilog- Public

    5-Stage RISC-V Pipelined Processor designed in Verilog HDL featuring Instruction Fetch, Decode, Execute, Memory Access, and Write-Back stages with RTL simulation and verification.

    Verilog

  2. My-portfolio My-portfolio Public

    HTML

  3. Industrial-Safety-Monitoring-System Industrial-Safety-Monitoring-System Public

    This project is a real-time Industrial Safety and Environmental Monitoring System built using ESP32, designed to detect hazardous conditions such as gas leakage, fire, and abnormal temperature or h…

    C++

  4. 8BIT-RISC-CPU 8BIT-RISC-CPU Public

    “Verilog-based 8-bit RISC processor with ALU, control unit, register file, and instruction memory. Designed and simulated in Xilinx Vivado.”

    Verilog