[darjeeling/verilator] Auto-generate Verilator chiplevel#30503
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Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit moves the dummy padring for Verilator from the testbench to the chiplevel, and replaces the connections to/from the DPI modules with hierarchical module references (XMRs). Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit adds the missing englishbreakfast chiplevel for Verilator, and adapts the tb to instantiate it. Like for earlgrey in the preceeding commits, this includes a Verilator-specific padring and a few additional branches in the shared chiplevel template. Since the combined tb and chiplevel did not include the real ast up until this point, the respective lint collateral for ast is linked to earlgrey. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
This commit is analogous to the preceeding ones but applies the changes to darjeeling. Signed-off-by: Florian Glaser <glaserf@lowrisc.org>
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Implements steps 3) and 4) as described in #30428 for darjeeling.
Depends on #30431