Add ethernet support on Shikra#709
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Merge Check Failed: No Change Task Found No associated change tasks found for CR 4570559 on any of the following entities: Entities:
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qli-2.0 GA Critical Fix |
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PR #709 — validate-patchPR: #709
Final Summary
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PR #709 — checker-log-analyzerPR: #709
Detailed report: Full report
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🔨 Build Failure Analysis — PR #709PR: #709
VerdictAll 3 errors are introduced by this PR. The patch series is missing helper function definitions and has an incorrect return statement. 📎 Detailed analysis: Full report |
🔨 Build Failure Analysis — PR #709PR: #709
VerdictAll 3 errors are introduced by this PR; 0 are pre-existing. 📎 Detailed analysis: Full report |
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@ayaan-anwar, please check build failure. |
Test Matrix
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This reverts commit 9c47fe9. Reason: this change is UPSTREAM_STALLED. Replace this with the RGMII rework for Shikra. Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
readl() returns a u32, and writel() takes a "u32" for the value. These are used in rgmii_readl()() and rgmii_writel(), but the value and return are "int". As these are 32-bit register values which are not signed, use "u32". These changes do not cause generated code changes. Update rgmii_updatel() to use u32 for mask and val. Changing "mask" to "u32" also does not cause generated code changes. However, changing "val" causes the generated assembly to be re-ordered for aarch64. Update the temporary variables used with the rgmii functions to use u32. [ upstream commit f54bbd3 ] Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/E1vM2mq-0000000FRTi-3y5F@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
The driver has a lot of bit manipulation of the RGMII registers. Add
a pair of helpers to set bits and clear bits, converting the various
calls to rgmii_updatel() as appropriate.
Most of the change was done via this sed script:
/rgmii_updatel/ {
N
/,$/N
/mask, / ! {
s|rgmii_updatel\(([^,]*,\s+([^,]*),\s+)\2,\s+|rgmii_setmask(\1|
s|rgmii_updatel\(([^,]*,\s+([^,]*),\s+)0,\s+|rgmii_clrmask(\1|
s|^\s+$||
}
}
and then formatting tweaked where necessary.
[ upstream commit 8192121 ]
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/E1vM2mw-0000000FRTo-0End@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Use read_poll_timeout_atomic() to poll the rgmii registers rather than open-coding the polling. [ upstream commit 9b60ba5 ] Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vM2n1-0000000FRTu-0js9@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
…tible Shikra's EMAC requires three additional clocks beyond the standard four (axi, axi-noc, pcie-tile-axi-noc) for NOC interconnect voting. Add the compatible string and extend clock-names with a oneOf variant for this seven-clock configuration. The AXI clock appears twice (as "stmmaceth" and "axi") because the stmmac core and the driver's NOC bulk-clock array each consume one reference; CCF refcounting makes this safe. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-1-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
… to void The return value is never checked by its sole caller and the speed validation duplicates a check higher up the call stack. Convert to void and remove the dead code. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-2-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
When "rgmii-id" is selected the PHY supplies both TX and RX delays, so the MAC must not add its own. The driver currently falls through to the generic DLL initialisation path which programs it to add a delay. Power down the DLL and set DDR bypass mode for RGMII_ID, then program the IO_MACRO via a new ethqos_rgmii_id_macro_init() helper. Also fix ethqos_set_clk_tx_rate() to not double the clock rate in bypass mode at 100M/10M, and remove RGMII_ID from the phase-shift suppression in ethqos_rgmii_macro_init() since RGMII_ID no longer reaches that path. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-3-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Some SoCs gate the EMAC's path to the System NOC behind dedicated clocks that must be enabled before the DMA can reach memory. Add ethqos_noc_clk_cfg and the corresponding fields in the driver-data and runtime structs so each compatible can declare its own set with per-clock rates. The clocks are acquired during probe and enabled/disabled alongside the existing link clock in ethqos_clks_config(). No functional change for existing compatibles. This will help us when we add support for Shikra. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-4-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys GMAC IP, similar to previous platforms. Register qcom,shikra-ethqos backed by a new shikra_data descriptor that enables the three NOC clocks required for DMA memory access and the 36-bit DMA address width. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-5-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Add the two Gigabit Ethernet controllers present on Shikra (ethernet0 at 0x5d00000, ethernet1 at 0x5d20000). Both nodes are left disabled; board files supply the PHY, pin-control, and queue configuration. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-6-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the first Gigabit Ethernet controller. Add pin-control for the RGMII and MDIO bus, a gpio-hog to assert the PHY power-enable GPIO at boot, and the board-level ethernet0 overlay with PHY and MTL queue configuration. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-7-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable the first Gigabit Ethernet controller. The board layout is identical to the CQM EVK. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-8-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Enable both Gigabit Ethernet controllers. Each port has a dedicated PHY with a gpio-hog to assert the power-enable GPIO at boot, pin-control for the RGMII and MDIO bus, and MTL queue configuration. Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-9-f0f4a1d19929@oss.qualcomm.com/ Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
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@quicAspratap / @shashim-quic , I had to rebase the PR again due to conflicts with Shikra DT and #619 . Can you please review it again? |
PR #709 — validate-patchPR: #709
Final Summary
Recommendation: Hold PR until upstream status is clarified. Either:
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PR #709 — checker-log-analyzerPR: #709
Detailed report: Full report
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Test Matrix
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This PR first reverts an UPSTREAM_STALLED change that was brought in for Talos.
The issue is resolved by the Shikra RGMII rework in the other commits which has been backported from LKML.
The changes have been tested on Shikra CQM, CQS and IQS boards.
To support the Shikra first-post patches, we also need to backport three upstream commits from https://lore.kernel.org/all/aR76i0HjXitfl7xk@shell.armlinux.org.uk/
Therefore, the commits are organized as:
Lore Link: https://lore.kernel.org/netdev/20260612-shikra_ethernet-v1-0-f0f4a1d19929@oss.qualcomm.com/
CRs-Fixed: 4570559, 4570571