EDAC/qcom: Make irq configuration optional#738
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On Shikra, the ECC interrupt configuration—enabling Tag/Data RAM interrupts and setting error thresholds—is already performed by the DSF (DDR System Firmware) before the kernel driver probes. Calling qcom_llcc_core_setup() would redundantly reconfigure these registers. Set the irq_configured flag in shikra_cfg to skip the redundant kernel-side interrupt enable register writes in qcom_llcc_core_setup(). Signed-off-by: Faiyaz Mohammed <faiyazm@qti.qualcomm.com>
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EDAC/qcom: Make irq configuration optional
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On Shikra, the ECC interrupt configuration—enabling Tag/Data RAM interrupts and setting error thresholds—is already performed by the DSF (DDR System Firmware) before the kernel driver probes. Calling qcom_llcc_core_setup() would redundantly reconfigure these registers.
Set the irq_configured flag in shikra_cfg to skip the redundant kernel-side interrupt enable register writes in qcom_llcc_core_setup().