Kaanapali CAMSS#741
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Add bindings for Camera Subsystem (CAMSS) on the Qualcomm Kaanapali platform. The Kaanapali platform provides: - 6 x CSIPHY (CSI Physical Layer) - 3 x TPG (Test Pattern Generator) - 3 x CSID (CSI Decoder) - 2 x CSID Lite - 3 x VFE (Video Front End), 5 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE Lite Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260601-kaanapali-camss-v14-1-e76f26aa6691@oss.qualcomm.com/
Add support for Kaanapali in the camss driver. Add high level resource information along with the bus bandwidth votes. Module level detailed resource information will be enumerated in the following patches of the series. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260601-kaanapali-camss-v14-2-e76f26aa6691@oss.qualcomm.com/
…e CSIPHY Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.4.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260601-kaanapali-camss-v14-3-e76f26aa6691@oss.qualcomm.com/
Add more detailed resource information for CSID devices along with the driver for CSID gen4 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. In this CSID version, RUP and AUP update values are split into two registers along with a SET register. Accordingly, enhance the CSID interface to accommodate both the legacy combined reg_update and the split RUP and AUP updates. Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260601-kaanapali-camss-v14-4-e76f26aa6691@oss.qualcomm.com/
Add Video Front End (VFE) version gen4 as found on the Kaanapali SoC. The FULL front end modules in Kaanapali camera subsystem are called TFEs (Thin Front End), however, retaining the name VFE at places to maintain consistency and avoid unnecessary code changes. This change limits the VFE output lines to 3 for now as constrained by the CAMSS driver framework. Kaanapali architecture requires for the REG_UPDATE and AUP_UPDATE to be issued after all of the CSID configuration has been done. Additionally, the number of AUP_UPDATEs should match the number of buffers enqueued to the write master while it's being enabled. Although the real time data from TFE goes through the RT_CAMNOC, we are required to enable both the camnoc_rt_axi and camnoc_nrt_axi clocks for the PDX_NOC, that follows both the RT and NRT NOCs in this architecture, to ensure that both of the latter are idle after reset. Co-developed-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com> Signed-off-by: Atiya Kailany <atiya.kailany@oss.qualcomm.com> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260601-kaanapali-camss-v14-5-e76f26aa6691@oss.qualcomm.com/
Add node for the Kaanapali camera subsystem. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260508-knp-camera-v1-1-a18e289163fd@oss.qualcomm.com/
Qualcomm Kaanapali SoC has three Camera Control Interface (CCI). Each controller contains two I2C hosts. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260508-knp-camera-v1-2-a18e289163fd@oss.qualcomm.com/
Define pinctrl definitions to enable camera master clocks on Kaanapali. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Hangxiang Ma <hangxiang.ma@oss.qualcomm.com> Link: https://lore.kernel.org/all/20260508-knp-camera-v1-3-a18e289163fd@oss.qualcomm.com/
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Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
PR #741 — validate-patchPR: #741
Final Summary
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PR #741 — checker-log-analyzerPR: #741
Detailed report: Full report
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aiquny
approved these changes
Jun 18, 2026
🔨 Build Failure Analysis — PR #741PR: #741
VerdictAll 40 unique undefined clock/power-domain constants are introduced by this PR due to a missing header file include. 📎 Detailed analysis: Full report |
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Add support for the RDI only CAMSS camera driver on Kaanapali. Enabling
RDI path involves adding the support for a set of CSIPHY, CSID and TFE
modules, with each TFE having multiple RDI ports. This hardware
architecture requires 'qdss_debug_xo' clock for CAMNOC to be functional.
Kaanapali camera subsystem provides:
6 x CSIPHY (CSI Physical Layer)
3 x TPG (Test Pattern Generator)
3 x CSID (CSI Decoder)
2 x CSID Lite
3 x VFE (Video Front End), 5 RDI per VFE
2 x VFE Lite, 4 RDI per VFE Lite
This series has been tested using the following commands with a
downstream driver for S5KJN5 sensor.
media-ctl --reset
media-ctl -V '"msm_csiphy2":0[fmt:SGBRG10/4096x3072]'
media-ctl -V '"msm_csid0":0[fmt:SGBRG10/4096x3072]'
media-ctl -V '"msm_vfe0_rdi0":0[fmt:SGBRG10/4096x3072]'
media-ctl -l '"msm_csiphy2":1->"msm_csid0":0[1]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
yavta --capture=20 -I -n 5 -f SGBRG10P -s 4096x3072 -F /dev/video0
CRs-Fixed: 4577008