cache: fix LLC AMO writeback collision; L2/L3 writeback, per-cache MPM classes, atomic tests

[tinebp]

Summary

Fixes a data-corruption bug in last-level-cache atomics, enables L2/L3 writeback with eviction tracking, restructures performance counters into per-cache MPM classes, and adds atomic benchmarks plus a Synopsys back-end flow.

Cache / AMO

• Fix different-line AMO writeback collision. The single LLC AMO writeback register could be clobbered by a second atomic to a different line before its writeback drained, silently dropping the write (tripped the VX_cache_amo writeback assertion under back-to-back AMOs). Replaced it with a depth-2 coalescing writeback queue: forwards in-flight values to dependent reads, coalesces same-line updates, and is deadlock-free (off the critical path — no timing or response-latency change). Validated 13/13 across base + dcache-writeback + 8-thread configs.
• L2/L3 writeback + eviction tracking with a new evictions field in cache_perf_t.
• AMO over L2+L3 uses a write-through L2 (-DVX_CFG_L2_WRITEBACK=0): every cache above the LLC must be write-through, else SC can spuriously succeed.

Performance counters (MPM)

• Split memory counters into per-cache MPM classes (icache / dcache / L2 / L3 / mem), selected by DCR.
• Folded VM/MMU (TLB/PTW) counters into the MEM class.
• Fixed vx_dump_perf gating so it no longer prints values for disabled features (e.g. VM) or unconfigured caches.

Tests & back-end flow

• OpenCL and HIP atomic benchmarks (atomicreduce, histogram).
• Synopsys post-synthesis layout / power / GDS flow (run_icc2.tcl, dump_power.tcl, powergrid.py, gds_render.py, SAIF filter).
• Cache synthesis DUT gains an AMO_ENABLE parameter (tracks the A extension by default).

Validation

• Full regression --regression --unittest --amo on both XLEN=32 and XLEN=64: 267/267 PASS.
• Standalone cache DUT synthesis closes timing at 300 MHz on Alveo U55C with AMO enabled.

🤖 Generated with Claude Code

[tinebp]

Pushed two regression fixes surfaced while validating the --dxa, --cache, and --debug suites on XLEN 32/64 with L2/L3 write-back now default:

• cache: aggregate the evictions counter in PERF_CACHE_ADD — the new evictions field in cache_perf_t wasn't summed in the per-cache aggregation macro, leaving those bits undriven in VX_cache_cluster. Verilator rejected every rtlsim build with PERF_ENABLE. (Caught by the dxa suite.)
• simx: track per-byte dirty bits for write-back cache writebacks — simx modeled a single dirty bit per line and wrote back the full line with an all-ones byte-enable. Under write-back L2/L3 with cross-cluster false sharing, the last writer clobbered words it never modified, corrupting the shared lower level (half-line baadf00d). Now mirrors the RTL DIRTY_BYTES behavior — only modified bytes propagate. (Caught by diverge over L2+L3 in the cache suite.)

Validated: XLEN=32 dxa 36/36 and cache 34/34 green. XLEN=32 --debug and all XLEN=64 suites still in progress.