[earlgrey/verilator] Integrate padring into chiplevel

[glaserf]

This PR is the first step towards auto-generating the Verilator chiplevels. These are currently all written by hand, which makes handling them during top/chiplevel restructuring like in #30076 a tedious and error-prone task.

The main challenge here is that Verilator uses a dummy padring, which does not contain any actual pads. Instead, the tb uses DPI modules to directly drive the various cio_* signals.

The strategy to achieve the above is therefore as follows:

1. Create Verilator-specific dummy padring(s), which the chiplevel then instantiates for the Verilator target (to be created in a follow-up PR, see below).
2. Connect to said padring through hierarchical module references (XMR) directly from the Verilator tb. This allows us to avoid a huge port list/map from said padring to the chiplevel boundary, which would inflate the shared chiplevel template greatly.
3. Create the Verilator target within the various top_<name>.hjson files, which takes care of any target-specific pinout of the "logic" toplevels (which now coincide with power domains).
4. Profit - delete the manually maintained Verilator chiplevels. Let topgen handle any updates, and auto-generate chip_<name>_verilator.sv.

This PR implements steps 1) and 2) for earlgrey.